Introduction to Ethernet Over SDH Technology

**Interface Specifications:
**　 SDH side: provides 1 x 155.52Mbps LVDS interface, supporting STM-1. On the receive side, the FPGA peripheral chip provides CDR clock recovery; on the transmit side, it directly connects to an external optical module;
　 Ethernet side: provides 1 full-duplex MII interface, connecting to an external PHY for interconnecting with access devices;
　 Provides 1 SPI interface for connection with the CPU
**Functional Specifications
**　 Supports 1 Virtual Concatenation Group (VCG), with VC4 granularity. VC4 mapping path: VC4->AU4
　 Supports standard LCAS (Link Capacity Adjustment Scheme) protocol
　 Supports ITU-T G.7041 GFP-F encapsulation protocol
　 The receive line interface completes serial-to-parallel conversion, frame search of STM1 data, descrambling of STM1 data, B1 error monitoring of STM1, and LOS/LOF status monitoring
　 The receive overhead processing section completes SOH overhead monitoring, AU pointer processing, and POH overhead monitoring
　 Provides AIS insertion function, with the insertion point at the exit of pointer interpretation
　 The transmit overhead section provides regeneration functions for POH overhead and SOH overhead
　 Provides AUPP function
　 Supports VC4 channel overhead insertion, extraction, and monitoring
　 Supports MII interface LoopBack function
　 Supports minimum packet length of 64 bytes and maximum packet length of 1916 bytes
　 Transparently transmits Ethernet packets; supports various statistics of Ethernet packets